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Schottky-type p-GaN gate Gallium Nitride High Electron Mobility Transistors (GaN-HEMTs) suffer from threshold voltage ( Vth ) instability phenomenon. Both positive and negative Vth shifts are reported when device undertakes the voltage bias, but the impact of this Vth instability phenomenon on device switching behaviors is less investigated. In this study, the drain-source voltage ( Vds ) induced bidirectional Vth shift in hard-switching condition is characterized and decoupled by an H-bridge based double-pulse test (DPT). Subsequently, the influence of Vth shift on switching behaviors is theoretically analyzed and demonstrated through SPICE simulation and experiment, showing how a positive shifted Vth can reduce the device turn-on commutation speed and increase the switching losses, and vice versa. The results suggest that the Vth instability phenomenon should be considered in accurate switching modeling.

This work investigates the power GaN-HEMTs switching behaviour differences resulted from usage of two gate driving configurations: single and split outputs. The analysis based on simulation and experimental results show that GaN-HEMTs could switch slower and cause higher switching losses when the split output configuration is used. This is because the output capacitance (Coss) of MOSFETs inside gate driver will be charged during the turn-on process of GaN-HEMTs, and this charging process can reduce the charging speed of input capacitance (Ciss) of GaN-HEMTs. Moreover, the gate resistance and parasitic inductance are the main parameters selected for analysis, and their distribution can amplify this effect by increasing the impedance ratio of turn-on and turn-off loop. This research provides guiding suggestions for gate driver and high-efficiency GaN-HEMTs power module design.

A new method is proposed in this paper to investigate the influence of current collapse effect on the Id−Vds characteristics of GaN-HEMTs in high voltage region based on a modified H-bridge circuit. The measured Id−Vds characteristics with and without the Vds bias are compared, which shows the effect of charge trapping due to the Vds bias on device Id−Vds characteristics in saturation region. These data will be used for a device model including the current collapse effect in full Id−Vds region.