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Schottky-type p-GaN gate Gallium Nitride High Electron Mobility Transistors (GaN-HEMTs) suffer from threshold voltage ( Vth ) instability phenomenon. Both positive and negative Vth shifts are reported when device undertakes the voltage bias, but the impact of this Vth instability phenomenon on device switching behaviors is less investigated. In this study, the drain-source voltage ( Vds ) induced bidirectional Vth shift in hard-switching condition is characterized and decoupled by an H-bridge based double-pulse test (DPT). Subsequently, the influence of Vth shift on switching behaviors is theoretically analyzed and demonstrated through SPICE simulation and experiment, showing how a positive shifted Vth can reduce the device turn-on commutation speed and increase the switching losses, and vice versa. The results suggest that the Vth instability phenomenon should be considered in accurate switching modeling.

High-frequency power converters need electromagnetic interferences filters using common and differential mode chokes with low parasitic capacitance to comply with the electromagnetic compatibility standards. This article proposes a modeling method of this capacitance and ways to minimize it. The studied components are ring core inductors with magnetic materials considered as perfect conductors or with high permittivity, such as nanocrystalline material and most Mn-Zn ferrite materials. In comparison to other work in the literature, the proposed approach takes into account the curvature of the turn, in addition to the coating of the core and the insulation layer of the wire. The hypotheses, used in this article to simplify the real geometry, are compatible with two-dimensional (2-D) approaches to compute the parasitic interturns and turn–core capacitances. These capacitances are evaluated thanks to the 2-D finite element method. The obtained model allows accurate evaluation of the effect of turn–core space on the parasitic capacitance, and enables to reduce its value with a limited impact on the volume of the magnetic component.

In order to model GaN-HEMT switching transients and determine power losses, a compact model including dynamic RDSon effect is proposed herein. The model includes mathematical equations to represent device static and capacitance-voltage characteristics, and a behavioural voltage source, which includes multiple RC units to represent different time constants for trapping and detrapping effect from 100 ns to 100 s range. All the required parameters in the model can be obtained by fitting method using a datasheet or experimental characterisation results. The model is then implemented into our developed virtual prototyping software, where the device compact model is co-simulated with a parasitic inductance physical model to obtain the switching waveform. As model order reduction is applied in our software to resolve physical model, the device switching current and voltage waveform can be obtained in the range of minutes. By comparison with experimental measurements, the model is validated to accurately represent device switching transients as well as their spectrum in frequency domain until 100 MHz. In terms of dynamic RDSon value, the mismatch between the model and experimental results is within 10% under different power converter operation conditions in terms of switching frequencies and duty cycles, so designers can use this model to accurately obtain GaN-HEMT power losses due to trapping and detrapping effects for power electronics converters

The new power GaN transistors allow to increase the operating frequency of converters to megahertz range, thanks to their low switching time that is of a few nanoseconds or less. This permits to reduce the values and the volume of the passive components, and enhance the power density of power converters. However, inductors needed for energy storage still take a large volume in converters compared with the others components, because of their weak energy density. Further, high frequency operation require low-losses magnetic materials. In this paper, a design method of PCB inductors is proposed. A flexible ferrite sheet is used to enhance the inductance value and ease the realization of custom-shape devices. The design method of the inductor is based on the optimization of the inductor volume taking into account thermal issues of the magnetic sheets. Also a simulation method is proposed to calculate the equivalent stray capacitance of the inductors. The proposed method provides a losses-volume trade-off that helps designers to optimize the inductor for their application.

Because of trapped charges in GaN transistor structure, device dynamic ON-state resistance RDSon is increased when it is operated in high frequency switched power converters, in which device is possibly operated by zero voltage switching (ZVS) to reduce its turn-ON switching losses. When GaN transistor finishes ZVS during one switching period, device has been operated under both reverse and forward conduction. Therefore its dynamic RDSon under both conduction modes needs to be carefully measured to understand device power losses. For this reason, a measurement circuit with simple structure and fast dynamic response is proposed to characterise device reverse and forward RDSon . In order to improve measurement sensitivity when device switches at high frequency, a trapezoidal current mode is proposed to measure device RDSon under almost constant current, which resolves measurement sensitivity issues caused by unavoidable measurement circuit parasitic inductance and measurement probes deskew in conventional device characterisation method by triangle current mode. Proposed measurement circuit and measurement method is then validated by first characterising a SiC-MOSFET with constant RDSon . Then, the comparison on GaN-HEMT dynamic RDSon measurement results demonstrates the improved accuracy of proposed trapezoidal current mode over conventional triangle current mode when device switches at 1MHz.

In order to better predict the high frequency switching operation of transistors in power converters, parasitic elements of these devices such as resistances, inductances and capacitances must be accurately evaluated. This paper reports on the characterization of a gallium nitride (GaN) packaged power transistor using S-parameters in order to extract the device parasitics. Because the transistor is packaged, a calibration technique is carried out using specific test fixtures designed on FR4 printed circuit board (PCB) in order to get the S-parameters in the transistor plane from the measurement. The proposed method is suitable for a wide range of power devices. In this work it is applied to an enhancement mode GaN High Electron Mobility Transistor (HEMT).The impact of junction temperature on drain and source resistances is also evaluated. According to characterization results, equation-based modeling is proposed for the non-linear parameters. The extracted parasitic elements are compared with reference values given by the device manufacturer.

This paper presents a PWM strategy for the cancellation of common-mode (CM) voltage generated by three-phase back-to-back two-level inverters. This method theoretically provides complete elimination of the CM voltage by synchronizing all the commutations of one converter with commutations of the other one, so that the overall resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is carried out on a 15kW motor drive prototype to validate the method effectiveness. Taking into account dead-time compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15dB reduction is achieved in a wide frequency range.

In order to study switching waveforms of a SiCJFET, its inter-electrode capacitances evolution is necessary when the power device is in linear region. In this paper, the reverse transfer capacitance Cgd is at first characterized by the multiplecurrent- probe method and afterwards validated by the measurement with an impedance analyzer. The output capacitance Coss is measured by the same method and compared with the single-pulse characterization, which shows a huge increase of the apparent capacitance values in linear region. The influence of the power transistor internal gate resistor is thus studied, revealing the inter-electrode capacitances measurement difficulties when the power device is in linear region. The characterization results are allowed to finely model the power transistor of which the switching behaviors are validated with the measurement in a buck converter.

With the advantage of high bandwidth and small insertion impedance, a current surface probe (CSP) used to measure switching current waveforms is presented in this paper. Its transfer impedance is characterized and validated by measuring an IGBT switching current that is compared with those obtained with a current probe (CP), a current shunt (CS) and a Hall effect current probe (HECP). Furthermore, by comparing with a CS to measure a GaN-HEMT switching current, it is shown that CSP is able to measure a switching current of a few nanoseconds, while it brings no influence on transistor voltage waveform measurement. The obtained results show that, the use of CSP brings little parasitic inductances in the measurement circuit and it does not bring the connection of the ground to the power converter, which is the case for the CS.

With the advantage of high bandwidth and small insertion impedance, a current surface probe (CSP) used to measure switching current waveforms is presented in this letter. Its transfer impedance is characterized and validated by measuring an IGBT switching current that is compared with those obtained with a current probe (CP) and a Hall effect current probe (HECP). Furthermore, by comparing with a current shunt (CS) to measure a GaN-HEMT switching current, it is shown that CSP is able to measure a switching current of a few nanoseconds, while it brings no influence on transistor voltage waveform measurement. The obtained results show that, the use of CSP brings little parasitic inductances in the measurement circuit and it does not bring the connection of the ground to the power converter.

This paper focuses on the modeling method of energy cables used in power conversion systems, in the aim of EMC simulation and overvoltage analysis. Based on the node-to-node functions method, A simple frequency-domain model with a reduced number of equivalent impedances is considered and applied to three-wire shielded cables, along with a fast identification method based on a cascaded-cell model. Even though the model eventually includes nonphysical virtual impedances, simulation in frequency domain provides accurate results when compared to equivalent experimental measurements, for various cable lengths and in short simulation times. Time-domain waveforms are then extracted from frequency-domain simulation and confirm the effectiveness of the proposed method in a wide frequency range up to 50 MHz. Finally, a good match has been found between experimental and simulation results of voltage overshoots on a buck power converter system.

The characterization of voltage-dependent capacitances of power semiconductor devices (diode, MOSFET, IGBT etc.) is very important for modeling their dynamic performances. A measurement method using two current probes has been developed to characterize inter-electrode capacitances of power devices while isolating the measurement devices from the high-voltage DC bias power source. Ciss and Coss are shown to be accurately measured while Crss is not convincing enough. Then an additional current probe is added to improve the method. Crss is shown to be well characterized by this three-current-probe method. This method has been validated using various technologies of semiconductor devices including silicon MOSFET and silicon carbide JFET. The inter-electrode capacitances of power devices can be safely and accurately measured with this multi-probe method even in high voltage.

Today, industry has not fully embraced the matrix converter solution. One important reason is its high control complexity. It is therefore relevant to propose a simpler but efficient modulation scheme, similar as three phase VSI modulators with the well-known symmetrical carrier-based ones. The modulation presented in this paper is equivalent to a particular Space Vector Modulation (SVM) and takes into account harmonics and unbalanced input voltages, with the same maximum voltage transfer ratio (86%). The aim of this work is to propose a simple and general pulse-width-modulation method using carrier-based modulator for an easier matrix converter control. Furthermore, a simple duty cycle calculation method is used, based on a virtual matrix converter. Finally, simulations and experimentations are presented to validate this simple, original and efficient modulation concept equivalent to matrix converter SVM.

This paper focuses on 3-level neutral-point-clamped (NPC) and flying-capacitor (FC) inverter topologies for variable-speed-drives. Although such topologies generate less conducted electromagnetic interferences than conventional two-level ones, their electromagnetic- compatibility (EMC) performance highly depends on their pulse-width-modulation (PWM) strategy. A comparative evaluation of several PWM strategies is performed, including a recently proposed method for NPC inverters, adapted to the specificities of the FC converter in this paper. Simulation results and experimental validations consolidate this comparative study.

In adjustable speed drive applications, the switching of the inverter semiconductors generates common mode currents as well as harmful overvoltages on the motor terminals when long cables are used. Consequently, bulky and expensive input and output filters must be used. This work aims at reducing these disturbances from their origin by using a three-level neutral-point-clamped (NPC) inverter controlled with a new pulse-width-modulation (PWM) strategy. Whereas previous common mode noise-reducing strategies usually generate higher overvoltages than conventional ones, the proposed PWM is able to manage both problems thanks to its internal degrees of freedom.

Pulse-width-modulated (PWM) voltage-source inverters are known to provoke high-frequency disturbances in motor-drive applications, especially when long cables are used. Indeed, the parasitic elements of the cable along with steep voltage transitions due to semiconductor switchings are responsible for conducted electromagnetic emissions as well as high overvoltages on the motor terminals. Therefore, several specific PWM schemes have been proposed in order to reduce these phenomena without requiring large passive filters. However, strategies which reduce common-mode currents (mainly conducted electromagnetic emission) tend to increase the overvoltages generated on the motor. This paper focuses on a new PWM strategy which reduces the common-mode currents generated by three-level inverters. It provides a control algorithm which makes sure that the motor overvoltages never exceed those of conventional strategies, while improving the electromagnetic-compatibility performance of the drive.

RÉSUMÉ. Cet article présente une nouvelle stratégie de modulation de largeur d’implusion destinée à réduire les courants de mode commun dans les applications de variation de vitesse utilisant un onduleur à trois niveaux de type neutral-point-clamped. Il détaille l’implantation de cette commande par un modulateur à porteuses en dents de scie permettant de contrôler les degrés de liberté apportés par la stratégie. ABSTRACT. This paper presents a new pulse-width-modulation strategy for the reduction of common-mode currents in adustable-speed-drive applications using a three-level neutral-pointclamped inverter. It is implemented through a saw-tooth carrier-based modulator which makes it possible to control the degrees of freedom provided by the strategy.

Adjustable-speed drives involve common-mode voltages, which generate common-mode currents flowing to the ground through stray capacitances of electric machines. These currents are known to provoke premature motor-bearing failures, as well as electromagnetic interferences disturbing neighbor electronic devices. Furthermore, high-voltage applications involve high levels of these conducted emissions, which must be lowered by using bulky and expensive filters. This paper aims at elaborating a new pulsewidth-modulation (PWM) strategy in order to reduce the common-mode currents generated by threelevel neutral-point-clamped inverters. The proposed strategy also provides the ability to balance the neutral point of the dc-bus capacitors. Experimental results both in time and frequency domains confirm that the new PWM improves the electromagneticcompatibility behavior of the drive compared with conventional strategies.

Power electronics converters generate conducted electromagnetic interference (EMI) over a wide frequency range. In order to prevent pollution of the electrical network and thus comply with electromagnetic compatibility (EMC) standards, it is necessary to install filters at the input side of converters. The optimal design of these filters requires modeling the entire energy conversion system and using the proposed models in circuit simulations (SPICE, etc.). Depending on whether the conversion system is already implemented or in the design stage, there are several modeling methods. When the system is already implemented, the method that treats the converter with its load as a black-box model, called “Terminal Modeling” is particularly suitable in this case. In this paper, we highlight its limitations and propose a gray-box model to enhance its accuracy and robustness up to 100 MHz.

This work investigates the power GaN-HEMTs switching behaviour differences resulted from usage of two gate driving configurations: single and split outputs. The analysis based on simulation and experimental results show that GaN-HEMTs could switch slower and cause higher switching losses when the split output configuration is used. This is because the output capacitance (Coss) of MOSFETs inside gate driver will be charged during the turn-on process of GaN-HEMTs, and this charging process can reduce the charging speed of input capacitance (Ciss) of GaN-HEMTs. Moreover, the gate resistance and parasitic inductance are the main parameters selected for analysis, and their distribution can amplify this effect by increasing the impedance ratio of turn-on and turn-off loop. This research provides guiding suggestions for gate driver and high-efficiency GaN-HEMTs power module design.

A new method is proposed in this paper to investigate the influence of current collapse effect on the Id−Vds characteristics of GaN-HEMTs in high voltage region based on a modified H-bridge circuit. The measured Id−Vds characteristics with and without the Vds bias are compared, which shows the effect of charge trapping due to the Vds bias on device Id−Vds characteristics in saturation region. These data will be used for a device model including the current collapse effect in full Id−Vds region.

High-frequency static converters requires inductors, common and differential mode chokes with a low equivalent parallel capacitance. To reduce it, this paper proposes first a semi-analytical model of this capacitance for inductors made with coated ring cores of nano-crystalline material. This model is based on 2D finite element method to compute the turn-turn and turn-core parasitic capacitances, taking into account loose windings. Then the total capacitance is computed thanks to an energetic approach. The model is validated against measurements performed on one core for several numbers of turns. Since the model shows that the capacitance is almost linear with the parasitic turn-core capacitance, specific devices are proposed to increase the distance between turns and core and thus decrease the capacitance. It is demonstrated that a small increase in overall volume allows to divide the equivalent parallel capacitance of a common mode choke by almost a factor of three while increasing its overall volume by only 37%.

The stray capacitance of inductors impairs their high frequency impedance. A semi-analytical model is proposed for inductors with conductive core to gain insight for ways to decrease stray capacitance for high frequency power electronic applications. First the elementary capacitances are simulated thanks to 2D electrostatic finite element method (FEM), then an energetic approach is used to compute the global stray capacitance. Experimental verification has been performed on a nanocrystalline ring core. Relative error to the measurement shows that the proposed model improves the accuracy, notably by properly taking into account spaces between turns and between turns and core.

The embedded energy conversion systems onboard vehicles impose strong constraints on power density (low weight and volume) and robustness. Several solutions can be used to achieve these objectives which consist in acting either on the design of the static converter or on the electric machine. In this paper, we propose to act on the two systems together. Thus, the increase in the power density of the converter will be achieved by using wide band-gap semiconductor power devices like the SiC or GaN. These components are very small and able to operate at high frequency, thus reducing the dimensions of passive components and of the cooling system used. To increase the reliability of the electric machine, a multiphase PMSM is used. In this paper, the proposed design method of the integrated GaN inverter into a machine is presented. It will be used for the realization of an integrated GaN inverter into a multiphase PMSM.

ElectroMagnetic Interference ( EMI) simulation of power converters helps engineers in the design process. In this paper, we describe a frequency - domain simulation method based on the Multi-Topology Equivalent Sources (MTES) model. The aim is to reproduce the non-linear behavior of power switches for a fast evaluation of the conducted EMI. The method performance is validated on a DC-DC converter.

This work proposes the electrothermal modeling of a packaged GaN power transistor in order to evaluate by simulation its performances in a 200 W – 1 MHz DC/DC converter. The complete electrical modeling of the high frequency converter using EM-circuit co-simulations is presented. After validation of the GaN transistor switchings waveforms and estimation of power losses, the operating temperature of the device is simulated and experimentally validated.

GaN transistors allow to design highly efficient and high power density converters due to their low conduction and switching losses. However, their very fast switching and low gate threshold voltage make them prone to gate instability issues. Furthermore, they suffer from current collapse issue that is notably known to impair on-state resistance, but other effects may be expected. This paper focuses on commutation behaviour and shows how current collapse also impacts the circuit stability by altering immunity to gate oscillations. Consequently, it is shown that the conventional double-pulse test (DPT) may not provide reliable assessment of the switching cell design. Theoretical analysis is carried out and a modified DPT test bench is proposed to evaluate the influence of current collapse on GaN converter circuit stability. The analysis is validated by experimental results based on the modified DPT setup.

In order to model GaN device dynamic RDSon value due to trapped charge, a measurement circuit to accurately measure device dynamic RDSon value under different OFF-state time and ON-state time is at first proposed. Based on measurement results, an analytical model with different cells is proposed to represent dynamic RDSon evolution. It is then represented as a behavioural voltage source to compensate device ON-state VDS voltage, which can be implemented easily into device manufacturer model in Spice-type electrical circuit simulator. The model is then validated by comparing with the measurement on device dynamic RDSon value of different switching frequencies, where the model agrees with experimental results on both transient and stabilized dynamic RDSon value.

GaN power transistors are drawing extensive research interest to increase power electronics systems efficiency and power density for electrical vehicles (EV). However, GaN devices suffer from current collapse, which results in shifted device static characteristics. In this paper, different measurement methods are proposed to investigate the influence of GaN transistor current collapse on device conduction and switching losses. By proposing a measurement circuit to accurately characterise GaN transistor dynamic RDS(on) , it is shown that device dynamic RDS(on) increases to 60% bigger than its static RDS(on) value when it is operated at 1MHz converter. By proposing a modified double pulse test fixture, device switching transition can be characterised when it is unbiased. Therefore, it is shown that current collapse increases device switching losses 20% bigger than unbiased condition. It is finally represented the influence of GaN device current collapse on device safe operation area in terms of operation current and frequency in EV-based power converters.

Inductors are required in switching power converters for energy storage. They take a large volume compared with the other components of converters because of their small energy density. Nowadays, the operating frequency of power converters increases to MHz range because of the fast switching time of the new power GaN transistors. This allows to reduce the volume of the required inductors. In this paper, a design based on the optimization of the volume of PCB inductor for GaN converter is proposed where a flexible ferrite sheet is used to realize the inductor. The proposed method takes into account the thermal issues of the ferrite sheet. The required inductance value for the GaN converter is chosen from a Losses-Volume curve.

Wide Bandgap (WBG) power devices show very good characteristics for high frequency operation in power converters, leading to a better power integration by reducing size and weight of passive components. Access parasitics such as resistances and inductances related to packaging and interconnections are important parameters to determine in order to better predict high frequency switching of WBG power devices. In order to design a 1 MHz hybrid GaN/SiC power converter, this paper reports on the characterization of packaged power devices such as Gallium Nitride (GaN) transistors and Silicon Carbide (SiC) Schottky diodes using S-parameters in order to extract the device parasitics. The method lays on a calibration procedure carried out using specific test fixtures designed on FR4 Printed Circuit Board (PCB). The proposed method has the objective to be suitable for a wide range of power devices.

Power electronics converters require energy storage components. The DC-DC converters need the magnetic storage components which take a large volume. The new power GaN transistors allow to increase the operating frequency of the power converter. The consequence is a reduction of the values and the dimensions of the passive components mainly the inductors. In this paper, a design method for PCB-integrated inductors is proposed. It is based on the optimization approach of inductors volume. The inductor is integrated on PCB with a flexible ferrite sheets used as magnetic material.

This paper presents a design method of a power converter that will be used to realize integrated adjustable speed drives. In order to reduce the dimensions of the static converter to integrate it to the machine, a converter based on gallium nitride (GaN) transistor is being developed. Indeed, GaN transistors packages are small and can operate at high switching frequencies which lead to the reduction of the passive component dimensions. To design this GaN-converter, the determination of parasitical elements of the gate and power circuits is necessary. In fact, these elements have a direct influence on transient behaviour, on the transistor losses and therefore on the cooling system. This work is achieved within the project CE2I (Intelligent Integrated Energy Converter).

Gallium Nitride (GaN) power devices developed these recent years are ideal candidates for high frequency power conversion, leading to a reduction of size, cost and weight of power converters. The design of these converters is based on simulations which require developing accurate models over a wide frequency range. This paper presents a new characterization method of GaN power transistors based on the extraction of devices small-signal parameters up to the gigahertz range using 2-port S-parameters measurements and dedicated characterization fixtures on printed circuit boards (PCB).

The subject of this paper is to propose a new design method of EMI filters that allows to minimize the volume of the common-mode inductor with consideration of core saturation issues. One of the main results of this study shows the impact of the switching frequency on the filter insertion loss and the volume of the coupled common-mode inductor depending on the length of the shielded cable. Then, the relationship between switching frequency and optimum inductor volume is investigated. Obtained results show that, depending on the cable length, an optimal switching frequency that allows to minimize the inductor volume can be determined.

The subject of this paper is to propose a design method of the EMI filters that allows to minimize the volume of the common mode inductor with consideration of core saturation issues. Inductor volume depends not only on its inductance value, but also on the relationship between the filter and its environment which can saturate the magnetic material due to many parameters, especially when the filter resonance frequency Fr is higher than the converter switching frequency Fs. One of these parameters is the converter duty cycle D. This study explains why it is more desirable to set Fr below Fs in order to reduce the coupled inductor volume while increasing the filter performances.

EMI filters are necessary in many applications in order to meet EMC standards, which significantly increase overall cost and volume mainly because of the common-mode choke. In this paper, a new method to calculate the minimum volume of the inductor is proposed. It takes into account core saturation issues that may greatly impact inductor volume. Consequently, it is shown that in some cases, increasing the inductance up to an optimal value can significantly reduce the filter volume in addition to further enhancing filter attenuation. Besides, determination of the filter resonance frequency with nano-crystalline material is worked out to support the analysis.

This paper focuses on pulse-width modulation (PWM) strategies that aim at cancelling common-mode (CM) voltage generated by power converters. In the typical use case of frequency converters, such strategies perform simultaneous switching between different inverter legs, so that their effects on CM voltage cancel each other. Doing so, the resulting CM voltage is reduced to mere commutation residues because simultaneous switching voltage waveforms may not be identical nor perfectly synchronous. Based on a PWM strategy that theoretically cancels the CM voltage generated by a variable-speed drive, this paper highlights the influence of desynchronization effects, commutation speeds, and different waveforms due to instantaneous currents, on the resulting CM voltage spectrum. Practical rules are derived in order to optimize the electromagnetic compatibility (EMC) performance of such PWM strategies.

This paper presents a PWM strategy for the reduction of common-mode (CM) voltage generated by variable-speed motor drives composed of two-level, three-phase active-front-end rectifier and three-phase inverter. This method theoretically provides complete elimination of the CM voltage by synchronizing all inverter commutations with rectifier commutations, so that the resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is provided on a 15 kW prototype to validate the method effectiveness. Taking into account dead-time compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15 dB reduction is achieved in a wide frequency range.

In the simulation of power electronics systems, for reasons of computing time and convergence, it may be necessary to use ideal components which generate ideal voltage switchings (steep edges). However, in reality, these voltage variations are far from ideal and to reproduce a voltage closer to reality, it is necessary to model these variations. This is especially important for the study of residual voltage obtained by simultaneous switching, which are present in PWM strategies developped to reduce the impact of the common-mode voltage generated by 3-phase inverters. This paper is focused on the required model accuracy, in order to take into account these residues obtained by the synchronization of switching voltages.

With the advantage of high bandwidth and small insertion impedance, a current surface probe (CSP) used to measure switching current waveforms is presented in this paper. Its transfer impedance is characterized and validated in the first time by measuring an IGBT switching current with a passive current probe (CP) and a Hall effect current probe (HECP). It is also shown that a return current beneath the PCB on which is put the CSP can reduce its transfer impedance. In the second time, the CSP is used to measure a GaN-HEMT switching current and the obtained results are compared with those measured with a current shunt (CS). The comparison of these results prove that CSP and CS are able to measure fast switching current (of the order a few nanoseconds). However, the advantage of the CSP is that it has no influence on the power device VDS voltage measurement. Also, the CSP brings less parasitic inductance in the commutation mesh than the CS and it does not have the ground connection drawback, which is the case for the CS.

The electrical power aboard aircraft tends to increase thanks to the progress in switched-mode power converters. The generalization of the use of power converters leads to EMI issues. The EMC standards compliance is often obtained by adding an EMI filter after a measurement on a prototype. Since prototyping is costly and time consuming, it is interesting to evaluate the level of EMI without prototyping. To achieve this goal, frequency-domain simulation is interesting, but classical method can not give a good representation of non-linear transition of the power switches. That is why a new frequency domain method is proposed. This method uses two equivalent generators topologies and combine them to obtain an accurate results. The combination is based on the use of validity functions associated with each topology. This paper is focused on the impact of the validity functions on the final result.

The characterization of voltage-dependent capacitances of power semiconductor devices is very important for modeling their dynamic performances. A measurement method using multiple current probes has been proposed to characterize inter-electrode capacitances of power devices. The advantage of this method is that it can isolate the measurement devices from the high-voltage DC bias power source. This method has been validated first on SiC JFET to obtain more capacitance dependency information both on high voltage of Vds and on Vgs , of which the latter is not included in datasheet. It is then applied on GaN HEMT, to prove its sensibility for a few picofarads capacitances measurement.

Since the early 1990’s, electrical energy tends to replace pneumatic and hydraulic energy aboard aircrafts. This is lead by MEA project and allows to reduce weight and volume of the actuators. But an increase of onboard electric energy leads to EMI issues. To comply with EMC standards, an EMI filter is often added to the electrical systems. In order to reduce the weight and volume impact of EMI filters, it is interesting to perform an optimization of the embedded electrical system at the design stage, based on EMC criteria, using a simulation approach. In order to perform these simulations, HF model of the system is necessary. Two approaches exist: either time-domain or frequency-domain simulations, each one having advantages and drawbacks. This paper presents a frequency-domain modeling method. The proposed method is based on the use of two linear equivalent noise generators topologies. The results obtained with the two topologies are combined, to obtain a good representation of power converters. This method increase the validity range of the simulation above 30MHz.

The increase of electric energy in aircraft leads to EMI issues, because the use of power electronics converters induces sharp voltage and current variations. EMC standards compliance often calls for EMI filtering. In order to simulate a system up to 50MHz it is necessary to use high frequency models of the studied system. The subject is to perform a frequency-domain analysis which induces short simulation times but cannot represent non-linear phenomena. In this paper, we propose EMI noise source models with topology combination through convolution of appropriate ”validity functions” to overcome this drawback. Comparison with time-domain simulations shows the validity of the proposed approach in a wide frequency range.

Understanding and characterizing complex EMI phenomena through accurate converters EMI noise emission models is a necessary first step for achieving an efficient filtering. Some of the existing EMI noise source models are only valid for specific applications. In order to study, by simulation the conducted emissions in PWM inverters with reasonable calculation duration, a behavioural model of EMI noise is necessary. In this paper, two EMI noise source models are proposed. It is used to represent the commutation transients of a power device via an equivalent current or voltage source.

Pulse-width-modulated (PWM) voltage-source inverters are known to provoke high-frequency disturbances in motor-drive applications, especially when long cables are used. Indeed, the parasitic elements of the cable along with steep voltage transitions due to semiconductor switchings are responsible for conducted electromagnetic emissions as well as high overvoltages on the motor terminals. Therefore, several specific PWM schemes have been proposed in order to reduce these phenomena without requiring large passive filters. However, strategies which reduce common-mode currents (main conducted electromagnetic emission) tend to increase the overvoltages generated on the motor. This paper focuses on a new PWM strategy which reduces the common-mode currents generated by three-level inverters. It provides a control algorithm which makes sure that the motor overvoltages never exceed those of conventional strategies, while improving the electromagnetic-compatibility performance of the drive

In adjustable speed drive applications, the switching of the inverter semiconductors generates common mode currents as well as harmful overvoltages on the motor terminals when long cables are used. Consequently, bulky and expensive input and output filters must be used. This work aims at reducing these disturbances from their origin by using a three-level neutral-point-clamped (NPC) inverter controlled with a new pulse-width-modulation (PWM) strategy. Whereas previous common mode noise-reducing strategies usually generate higher overvoltages than conventional ones, the proposed PWM is able to manage both problems thanks to its internal degrees of freedom.

A new carrier-based PWM for the reduction of common mode currents applied to Neutral Point Clamped inverters

Inverters used in adjustable speed drives create common mode voltages with high dv/dt transitions resulting in high frequency common mode currents which flow to the ground through stray capacitances. These common mode currents are known to damage the bearings of electric machines and cause malfunctions in other surrounding electronic devices, and therefore need to be confined by using bulky and expensive electromagnetic compatibility (EMC) filters . The presented work focuses on the three levels neutral-point-clamped (NPC) inverter and proposes a new pulse width modulation (PWM) strategy for the reduction of common mode currents by lowering the number of step variations of the common mode voltage. Unlike previous strategies, this carrier-based PWM pays attention to the real phenomena involved in the generation of common mode currents so as to efficiently reduce them by avoiding dead time effects . The new strategy has been implemented in a 20 kVA prototype and the experimental results presented in this paper confirm its best EMC behavior compared with classical PWM.

Les convertisseurs d’électronique de puissance génèrent des perturbations électromagnétiques conduites dans une large bande de fréquences. Afin d’éviter de polluer le réseau électrique et respecter ainsi les normes de compatibilité électromagnétique (CEM), il est nécessaire d’installer des filtres à l’entrée des convertisseurs. Le dimensionnement optimal de ces filtres CEM nécessite une modélisation de l’ensemble du système de conversion d’énergie puis l’utilisation des modèles proposés dans des simulations de type circuit (SPICE …). Selon les cas où le système de conversion est déjà réalisé ou au stage de conception, il existe plusieurs méthodes de modélisation. Lorsque le système est déjà réalisé, la méthode, qui considère le convertisseur avec sa charge comme un modèle boîte noire, appelée “Terminal Modeling” est particulièrement adaptée dans ce cas. Dans ce papier, on met en évidence ses limites puis on propose un modèle de type boîte grise afin d'améliorer sa précision et sa robustesse jusqu'à 100MHz.

La montée en fréquence des convertisseurs statiques de puissance oblige à dimensionner les filtres de compatibilité électromagnétique en prenant en compte les éléments parasites de ces derniers. L’objectif est alors d’obtenir un modèle circuit de la bobine de mode commun sur une large plage de fréquence (150 kHz à 30 MHz ici), puis d’utiliser ce modèle pour dimensionner une bobine de mode commun pour le respect d’une norme (DO-160-B ici). L’équivalence circuit du modèle de Debye de la perméabilité magnétique complexe permet de simplifier le dimensionnement de l’inducteur avec la prise en compte de la chute de perméabilité avec la fréquence. La solution semi-analytique de la bobine optimale prend en compte la non-saturation du noyau, et le remplissage de la fenêtre de bobinage, le tout avec un coût de calcul modéré. La géométrie optimale est alors utilisée dans un modèle de la capacité parallèle équivalente de l’inducteur pour prédire avant réalisation sa valeur et la maintenir en deçà du maximum calculé pour le respect de la norme.

Les capacités parasites des bobines impactent leur impédance à haute fréquence. Un modèle semi-analytique de la capacité parasite équivalente pour des bobines à noyau conducteur (nanocristallin) est proposé pour expliquer son origine et la réduire, notamment pour des applications de filtrage pour la compatibilité électromagnétique (CEM) à haute fréquence. Une approche énergétique est utilisée pour calculer la capacité parasite équivalente à partir du nombre de tours et de la valeur des capacités parasites élémentaires issues de simulation éléments finis. Les erreurs relatives par rapport aux mesures montrent que le modèle proposé améliore la précision de la prédiction par rapport aux modèles classiquement utilisés dans la littérature et prend en compte correctement l’évolution avec le nombre de tours et les espacements inter-spires, et spire-noyau.

Les systèmes électriques embarqués dans les véhicules doivent satisfaire aux exigences normatives de compatibilité électromagnétique. Afin de s’en assurer, l’émission des interférences électromagnétiques est caractérisée par des méthodes de mesure normalisées. Les paramètres du récepteur de mesure, tels que la bande passante de résolution et le mode de détection, influent directement sur les résultats. De ce fait, pour réaliser des confrontations entre résultats de simulation et de mesure, la réponse du récepteur de mesure doit être prise en compte. La méthode proposée permet de modéliser cette réponse avec un faible temps de calcul. Le principe utilisé repose sur la transformée de Fourier à court terme et fournit des résultats en détection crête, quasi-crête et moyenne.

Les systèmes électriques embarqués dans les véhicules doivent satisfaire aux exigences normatives de compatibilité électromagnétique. Afin de s'en assurer, l'émission des interférences électromagnétiques est caractérisée par des méthodes de mesure normalisées. Les paramètres du récepteur de mesure, tels que la bande passante de résolution et le mode de détection, influent directement sur les résultats. De ce fait, pour réaliser des confrontations entre mesure et simulation, la réponse du récepteur de mesure doit être prise en compte. La méthode proposée permet de modéliser cette réponse. Le principe utilisé repose sur la transformée de Fourier à court terme et fournit des résultats en détection crête, quasi-crête et moyenne.

Ce papier propose une nouvelle méthode pour estimer les permittivités relatives qui permettent de calculer la capacité parasite des bobines toriques utilisées dans le filtrage CEM. Cette méthode est basée sur une association d’essais expérimentaux et des simulations éléments finis 2D sur FEMM permettant de déterminer les permittivités relatives des noyaux magnétiques en prenant en compte une éventuelle anisotropie. Ensuite, ce même logiciel a été utilisé pour estimer la capacité parasite équivalente de la bobine avec une faible erreur relative indépendamment du nombre de spires.

Les composants de puissance à base de GaN présentent un fort potentiel pour le développement de convertisseurs statiques fonctionnant à hautes fréquences. Les principales propriétés de cette filière technologique conduisent à une réduction de la taille, du poids et du volume des convertisseurs d’énergie. La conception de ces convertisseurs hautes fréquences (HF) repose sur des simulations nécessitant des modèles de composants actifs très précis. Afin d’obtenir ces modèles, une phase de caractérisation permettant d’obtenir les différents paramètres du modèle est nécessaire. Ce travail présente une méthode de caractérisation des transistors de puissance GaN basée sur la mesure de paramètres S à l’aide de dispositifs d’adaptation sur circuit imprimé ainsi que des mesures en régime pulsé.

Ce travail de thèse s’inscrit dans le cadre de la collaboration entre l’IEMN et le L2EP sur la thématique de la montée en fréquence des convertisseurs statiques pour l’intégration de puissance. Les transistors de puissance à base de Nitrure de Gallium (GaN) offrent la possibilité de commuter de fortes puissances (au- delà d’1 kW) à hautes fréquences (au-delà d’1 MHz), permettant ainsi de réduire le volume des composants passifs des convertisseurs d’énergie. La conception des convertisseurs hautes fréquences par simulation nécessite de disposer de modèles de composants de puissance précis et valides sur une large plage de fréquence. Les techniques classiques de caractérisation et modélisation utilisées en électronique de puissance sont limitées en bande de fréquence et ne permettent pas de modéliser de façon précise tous les effets intrinsèques aux composants en hautes fréquences. L’objectif de ce travail est d’adapter les techniques utilisées dans le domaine de la caractérisation hyperfréquences pour la modélisation d’un transistor de puissance GaN. Dans le cadre de cette étude, le transistor GS66502B 650V/7.5A de type GaN HEMT sera utilisé pour la mise en place de notre méthode. La plage de fréquence visée pour la modélisation est 1 MHz – 1 GHz.

Ce papier propose une nouvelle méthode de dimensionnement de la bobine couplée du filtre de mode commun qui minimise son volume tout en tenant compte de la contrainte de la saturation du noyau magnétique. Les résultats de simulations obtenus, validés expérimentalement, montrent que, dans certains cas, augmenter la valeur de l’inductance jusqu’à une valeur optimale permet de réduire le volume du noyau magnétique tout en améliorant les performances des filtres CEM.

Les filtres CEM sont largement utilisés dans les convertisseurs statiques afin de respecter les normes CEM, ce qui augmente considérablement le volume et le coût des installations à cause de la bobine de mode commun. Ce papier présente une nouvelle méthode qui permet de calculer le volume minimal de la bobine couplée de mode commun en tenant compte des contraintes de la saturation du matériau magnétique. Les résultats obtenus montrent que, dans certaines applications, augmenter la valeur de l'inductance jusqu'à une valeur optimale permet de réduire le volume du noyau magnétique tout en améliorant l'atténuation du filtre.

Afin d’étudier les commutations du transistor SiC-JFET “ Normally-off ”, l’évolution des capacités inter-électrodes est présentée dans ce papier lorsque le composant est en régime désaturé. La capacité de contre-réaction Cgd est tout d’abord caractérisée par la méthode des pinces de courant et ensuite validée par la mesure à l’aide d’analyseur d’impédance. Ces méthodes de caractérisation sont ensuite appliquées à la mesure de la capacité de sortie Coss, et montrent une forte augmentation de capacité apparente en régime désaturé. L’influence de la résistance de grille interne est alors étudiée, soulevant la problématique de mesure des capacités inter-électrodes des composants de puissance lorsque le canal conduit. Les résultats de caractérisation permettent finalement la mise en oeuvre d’un modèle comportemental dont le comportement en commutation est validé par des mesures sur un hacheur buck.

Dans le domaine de la variation de vitesse, les perturbations conduites de mode commun sont les plus difficiles à maîtriser du fait des multiples chemins de propagation possibles. Ces perturbations peuvent être réduites à l’aide de filtres passifs qui sont généralement très volumineux. Une solution pour réduire la taille de ces filtres consiste à réduire les perturbations de mode commun à la source, à savoir la tension de mode commun induite par le convertisseur. C’est dans cette optique que s’inscrit cet article qui étudiera une stratégie de modulation permettant la synchronisation de tous les fronts de tension dans une structure onduleur-redresseur entièrement commandé. Avec l’utilisation de cette stratégie de synchronisation que l’on qualifiera de synchronisation totale (ST), il est possible de réduire la tension de mode commun à de simples résidus issus des commutations des différents bras de la structure. Dans cet article seront présentés les développements de la stratégie de synchronisation totale en vue d’une généralisation à tout point de fonctionnement du variateur ainsi qu’une étude de l’impact des résidus liés aux commutations des différents bras de la structure sur le contenu spectral de la tension de mode commun.

Cet article présente une amélioration des performances d’un convertisseur matriciel par utilisation de degrés de liberté naturellement accessible au niveau de la matrice de conversion. Ces améliorations sont réalisées à partir d’un modulateur simple et synthétique, basé sur l’introduction d’un convertisseur virtuel. On présente tout d’abord une méthode de généralisation de la matrice de conversion obtenue avec une modulation classique. Cette matrice est modifiée afin d’induire la modification de la phase de roue libre. Un choix approprié est effectué et on réalise alors l’étude des pertes silicium du convertisseur. Les performances du convertisseur utilisant la modulation proposée et celle utilisée classiquement dans la littérature sont comparées. La méthodologie de calcul des pertes silicium est présentée ainsi que la validation fonctionnelle de cette nouvelle modulation par des relevés expérimentaux réalisés sur un prototype laboratoire.

Cet article présente une nouvelle stratégie de modulation de largeur d’implusion (MLI) destinée à réduire les courants de mode commun générés dans les applications de variation de vitesse utilisant un onduleur à trois niveaux de type neutral-point-clamped (NPC). Il détaille le principe de la commande et son implantation dans un processeur par un modulateur à porteuses en dents de scie. Celui-ci permet de contrôler les degrés de liberté apportés par la stratégie.

Cet article présente le fonctionnement des onduleurs Z-source. Ils utilisent un réseau d’impédance pour coupler l’onduleur à la source de tension continue. Ce réseau d’impédance est constitué d’une structure L C hybride croisée. Il permet à l’onduleur d’amplifier la tension de sortie grâce à une commande spécifique, ce qui le rend équivalent à la mise en cascade d’un hacheur survolteur avec un onduleur classique. L’étude du principe de fonctionnement ainsi qu’une comparaison avec une structure classique équivalente montreront les limites de cette structure récemment introduite.

It is well known that GaN device dynamic ON-state resistance would increase when device is operated in high frequency power converter, where device is possibly operated by zero voltage switching (ZVS) to reduce turn-ON switching losses. When device finishes ZVS during one switching period, it has been operated under both reverse and forward conduction. Therefore, its dynamic Rdson needs to be carefully measured under both conduction modes to understand device power losses. For this reason, a measurement circuit with simple structure and fast dynamic response will be presented to measure device reverse and forward Rdson. In order to improve measurement sensitivity, a trapezoidal current mode will also be presented to characterise device Rdson under almost constant current, which resolves measurement circuit sensitivty issue caused by parasitic inductance and measurement probes deskew.

GaN transistors have been attracting much attention in recent years due to their significant benefits on the reduction of conduction and switching losses in power converters. However they suffer from current collapse effect due to trapped charges that notably impairs on-state resistance, as largely discussed in literature. This work focuses on commutation and shows that current collapse also impacts the switching waveforms of GaN transitors, notably increasing switching losses at turn-on. The influence on gate instability at turn-off is also discussed, showing that conventional double-pulse test may be misleading when measuring switching transitions. Theoretical analysis is validated by experimental measurements using a modified double-pulse test to evaluate the influence of current collapse on switching waveforms.

A control method implemented for an electric motor control installation, the control installation including a first converter having controlled switching arms for applying first voltage edges to a first electric motor connected to the first converter by first output phases, a second converter having controlled switching arms for applying second voltage edges to a second electric motor connected to the second converter by second outlet phases, the control method including a step of synchronising first voltage edges with second voltage edges in order to minimise the common-mode currents generated by the installation.

The method involves performing synchronization and phasing steps permitting to implement control voltage vector at frequency and a turning voltage vector defined by exact connection between three input phases (u, v, w) and three output phases (a, b, c) of a speed variator. The control voltage vector is amplified beyond 87 percent of amplitude of input voltages (Vun, Vvn, Vwn) and until reaching amplitude of the turning voltage vector, where the input phases are connected to an alternative voltage source applying the input voltages between the input phases and the output phases. An independent claim is also included for a direct matrix converter type speed variator comprising a control unit for amplifying a control voltage vector.

méthode de modulation permettant de limiter les perturbations CEM engendrées par la modulation des convertisseurs MLI

L’énergie électrique transite par des convertisseurs électroniques de puissance dont la réduction d’encombrement représente un enjeu majeur, en particulier dans les systèmes embarqués. Cette problématique se répercute principalement sur les contraintes de dissipation thermique et de filtrage passif dans une large plage de fréquences. Elle nécessite alors des actions aussi bien sur les composants de puissance actifs et passifs que sur les structures et la commande des convertisseurs statiques qui les emploient. Les travaux de recherche exposés dans ce mémoire présentent des avancées obtenues par action sur les topologies et stratégies de commande des convertisseurs, réduisant les contraintes de filtrage liées à la pollution harmonique du réseau et aux perturbations électromagnétiques (PEM) conduites à hautes fréquences (HF). Pour limiter les pertes et le volume des éléments de dissipation et de lissage, des composants semi-conducteurs à large bande interdite (WBG) sont employés, apportant néanmoins de nouvelles contraintes sur le plan de la compatibilité électromagnétique (CEM). Des travaux de caractérisation et de modélisation des composants jusqu’au système complet permettent alors l’analyse par simulation des PEM se propageant dans l’ensemble d’une chaîne de conversion. Enfin, ces développements permettent la mise en œuvre robuste des composants WBG au sein de convertisseurs compacts qui bénéficient, à la fois, de méthodes de commande optimisant leur comportement HF et d’un dimensionnement à volume minimal des bobines de mode commun associées. Ces recherches mettent en évidence les interactions entre les travaux menés à l’échelle des composants d’une part, et de la structure et la commande des convertisseurs d’autre part. Les perspectives proposées visent à développer des actions combinées partant des composants de puissance et s’orientant vers la conception de systèmes complexes multiconvertisseurs compacts, « propres » et efficaces.

It is proposed a novel GaN-HEMT modelling method by using S-parameters to characterise device inter-electrode capacitances and terminal contact resistances.Afterwards, the model is implemented into virtual prototyping software. By co-simulation with electromagnetic models generated of the VP software, device switching waveforms are then obtained and they are compared with commercial ADS software and experimental measurement.

This research work is supported by center research exchange scheme between the University of Nottingham and University of Lille in France. It is proposed an improved characterisation method to measure GaN-HEMT dynamic ON-state resistance quickly (less than 100 nanoseconds) after device OFF-state to ON-state transition (in comparison to 1 microsecond of authors' previous work). GaN-HEMT dynamic ON-state resistance is thus evaluated in megahertz high frequency switching power converter when device is in soft switching (in comparison with 10kHz hard switching power converter of previous work) to compare with device static ON-state resistance.

Common mode voltages generated by adjustable-speed drives create common mode currents which damage electric machines and require expensive filters. Usual ways to cope with this issue are based mainly on filtering and designing appropriate converters. However, recent development on power electronics shows that solutions can also be developed on PWM strategies. Thus, the presented work aims at elaborating a suitable PWM strategy for the reduction of common mode currents in three levels Neutral-Point-Clamped (NPC) inverters. The proposed new PWM appears to be a compromise solution between the quality of low frequency voltage supply (output Total Harmonic Distortion: THD) and high frequency conducted emissions (Electro-Magnetic Compatibility: EMC). The principle of the method is to lower the number of variations of the common mode voltage by introducing simultaneous commutations, so that the common mode voltage is not affected during the switching. As a consequence, the associated common mode current of the commutations is cancelled. The particularity of this PWM strategy, compared with previous ones, is that the double commutation is permanently controlled and adapted so as to ensure its perfect synchronism by avoiding dead time effects. The novel strategy has been implemented on an experimental bench using a carrier-based modulator and validated through common mode current measurements in both temporal and frequential domains. This research results from a co-operation between Schneider Electric, STIE (Schneider Toshiba Inverter Europe) and the L2EP (Laboratoire d’Electrotechnique et d’Electronique de Puissance de Lille), and focuses on the theme of adjustable-speed drives with reduced electromagnetic emissions. It is financed by Schneider Electric for one part and by the French State and the Région Nord-Pas-de-Calais for the other part. The new PWM strategy has been the subject of a patent deposit from Schneider Electric in 2006.

This chapter focuses on the control of single-phase and three-phase voltage-source inverters that are widely used for the conversion of AC electrical energy. Pulse-width modulation is discussed as a means of generating reference voltages based on inverter discrete states. Vector representation is introduced for proper analysis of inverter states selection, and carrier-based modulation is considered for simple control implementation. Available degrees of freedom are discussed and classical control methods are presented along with their main limitations and trade-off, exposing the impact of control choices with regard to application constraints.

Parmi les convertisseurs d’électronique de puissance, les variateurs de vitesse utilisés pour l’alimentation des machines électriques sont source de perturbations électromagnétiques à haute fréquence telles que les courants de mode commun et les surtensions aux bornes des moteurs. Le travail porte sur la réduction de ces perturbations par l’emploi d’un convertisseur multiniveaux associé à de nouvelles lois de commande rapprochée. Après un état de l’art des méthodes d’atténuation existantes, l’onduleur à trois niveaux de type neutral-point-clamped (NPC) est retenu comme structure de conversion continu-alternatif et une nouvelle stratégie de modulation de largeur d’impulsion (MLI) est développée en vue de réduire les courants de mode commun générés par l’onduleur. Les phénomènes entrant en jeu dans les commutations des interrupteurs de puissance sont analysés et modélisés afin d’établir des contraintes de commande permettant de maximiser les performances de la MLI proposée. Parallèlement, l’utilisation de câbles longs entre le variateur et la machine soulève une contrepartie vis-à-vis des surtensions moteur qui est maîtrisée par l’exploitation adéquate des degrés de liberté de la nouvelle MLI. Enfin, la problématique de régulation du point milieu capacitif du bus continu est abordée. La stratégie proposée est implantée expérimentalement par l’intermédiaire d’une modulation naturelle par porteuses, et les résultats de mesure montrent un gain de cinq décibels sur les courants de mode commun par rapport aux stratégies classiques tout en limitant les surtensions générées aux bornes du moteur et en assurant l’équilibrage du bus continu.