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LABORATORY OF ELECTRICAL ENGINEERING AND POWER ELECTRONICS

Research – Development – Innovation

Séminaire, OMN, Dr. Shuai Yan, Chinese Academy of Science, 7 juin 2019

Nous accueillons depuis le 17 juin, Dr. Shuai Yan de l’Institute of Electrical Engineering, Chinese Academy of Science.

Dr. Shuai Yan effectuera un séminaire le Jeudi 27 Juin à 14h sur le thème:

Model Order Reduction with POD/PGD and Related Applications in Computational Electromagnetics

Date : Jeudi 27 juin 2019, 14h
Lieu : IUT A Amphi 1A12

Modern industrial development brings new challenges to computational electromagnetics by introducing extremely computationally intensive problems and the needs of real-time simulation. Model order reduction can help with tacking these challenges from two perspectives. One is to solve the problems with less computational cost in time and memory, another is to build a compact parametric model from an “offline process” which can be used to achieve a fast solution during an “online process”. POD and PGD are two important MOR techniques that attracts much attention in recent years. In this presentation, I will discuss the implementation of POD and PGD in both static and high-frequency problems. Issues including complex domains, high dimensionality as well as adaptive algorithms will be addressed.

 

Dr. Shuai YAN (Institute of Electrical Engineering, Chinese Academy of Science)

Shuai Yan received the B.S. degree in Mathematics and Applied Mathematics from Beijing Normal University in 2007 and the M.S. degree in Computational Mathematic also from Beijing Normal University in 2010. She received the Ph.D. degree in Computational Optics in University of Erlangen-Nuremberg in Germany, 2014. After that, she joined the Chinese Academy of Science as an Associated Researcher. She has published more than ten papers in international journals. Her current research interests are model reduction techniques for full wave analysis and optimization of high frequency RFID systems and also efficient solvers for multi-physics analysis in integrated circuit design.